Runtime for RISC-V softcore

General
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1

I’d like to create a custom runtime for the Microchip MI-V softcores. They are not 100% supported by the GNAT runtimes, since they have no support for the “c” (compressed instructions) extension. So rv32-im is missing the “a” and rv32-imac has the additional “c”. Of course the code runs with rv32-im anyway and “a” is typically not required without SMP (as far as I know).

Nevertheless I like to use the CoreUARTapb peripheral for standard Put, so a custom runtime makes sense.

Now my main issue: The core can be configured with or without FPU. Since the only difference between rv32-imac and rv32-imafc is the runtime.xml with the the -march and -mabi compiler flags, I’d like to make those flags configurable using alire. Can I just remove the runtime.xml and put the switches into the runtime_build.gpr?

2

Switches in runtime.xml are used for all compilation units, while from runtime_build.gpr for runtime units only.

PS. I’m trying to evaluate another way to manage runtimes, see

Announce: bare board runtime generator version 0.0.1

3

I haven’t tried, but you could maybe potentially modify the runtime.xml to have the choice there, based on the alire’s config gpr file. The XML is runtime.xml is really just a template for a .gpr file, so I would think it would allow you to put in case statements and such? Again, I haven’t tested, but something to look at.