SweetAda on NEORV32

Hi all.

I’ve created a NEORV32 target platform in SweetAda (GitHub - gabriele-galeotti/SweetAda: Ada-language framework).

NEORV32 (GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.) is a RISC-V SoC implementation in VHDL, suited for FPGAs.

The setup is blatantly primitive and runs under simulation by means of GHDL, outputting a welcome message inside the simulated UART console. This setup is still WIP, I have to properly integrate the build
machinery with that of the NEORV32 environment.

So far I have no FPGA hardware (besides the time) ready to create a real implementation, so if someone is using NEORV32 on real hardware, and is willing to test, this will be very interesting. Just a OK/KO flag. The current setup needs only UART clocking parameters in the CTRL register, which I suppose it depends on the actual clock configuration. In the meantime I will try to develop things inside the simulated GHDL environment.

Best regards,

1 Like

That’s interesting.
If I had time, I would try it immediately.

Don’t worry.

Time depends if one has already a pretty standard hardware (basic things + UART,
at least) ready to run. Then, it’s just a matter of injecting the ROM-image-like
VHDL file produced by SweetAda, that describes machine instructions, replacing the
original one.

BTW, in the meantime I’ve created an automated procedure that does everything
in a transparent way, without cumbersome operations. Things look ok, and the code
now runs through a loop that writes the mtime timer counter continuously.