Hi.all !
Some TLALOC compiled programs (DIS_BONJOUR and some others) have been executed on a vhdl specification of the TAHX processor which implements an OoO stack machine with a custom homebrew binary ISA (the LLIR_hardware_support_V8.txt giving HX executables).
Optimization of the machine is underway and some exploration of the ghdl-yosys-OpenROAD path has begun to assess if the TAHX processor could be implemented in silicon with IHP MPW 130nm process.
Hi,
All this seems interesting but is very cryptic.
Can you explain what TLALOC, TAHX, OoO, LLIR… mean ?
Hi DrPi !
TLALOC is the Ada83 compiler written in Ada83 (self-hosted bootstrapped).
The compiler uses fasmg assembly macros to produce x86_64, arm64, riscv64 ELF binaries, or PE32+ Windows and UEFI executables.
But fasmg also allows for static analysis of the LLIR (Low Level Intermediate Representation) with a special codi_SX fasmg backend, and execution dynamic analysic with an interpreter TX_RUN reading a TX research executable produced with yet another codi_TX macros backend.
From those studies, an ISA implementing the Ada83/TLALOC LLIR and derived from the common LLIR of all targets has been designed with the intention of executing the binary on a real edge cutting stack processor (TAHX : TLALOC Ada Hardware eXecutor).
TAHX is a stack processor with stack slots renaming to allow for Out of Order (OoO) execution. It has a working vhdl specification and even some floor-planning and partial OpenROAD synthesis.
The following post gives the GitHub paths to repositories.
Hi VMo,
Thanks for clarifying.
This is effectively a very interesting topic.
Hi.all !
Some news about the TLALOC chain. I recall that the objective is having an open and fully auditable Ada 83 software/hardware stack from CMOS transistor cells to the Ada 83 compiler. Nothing hidden in the electronics or the software.
Also in the project is having a processor supporting Ada checks and language specifics without sacrificing performance.
I spent most of my available time on the development of the TAHX processor which executes the LLIR V8 specification (Ada-83-TLALOC-TAHX/TAHX_1_Processor_Reference_Manual_V8.pdf at cebfb360e8e68d1c1eff3200b882d1523630bb05 · Team-Ada-83-TLALOC/Ada-83-TLALOC-TAHX · GitHub).
A vhdl model of an Out of Order (OoO) processor demonstrated by ghdl simulation that 3 instructions per cycle (IPC=3) was achievable.
But the ghdl simulation is one thing, synthesizing and routing a real silicon die is quite another task. So I decided to start implementing an In Order (InO) TAHX processor. his choice also has the advantage to produce a predictible execution with precise interrupts, an aspect interesting for Ada. Out of order processors pose problems regarding predictibility.
TAHX_InO executes exactly the same ISA as TAHX_OoO but I succeeded in synthesizing the vhdl with YOSYS and hierarchically routing five macros with LIBRELANE/OPENROAD targeting the IHP (Leibniz Institute) 130 nm CMOS technology. For the moment the TAHX_InO clock is a conservative 10 MHz only and the present IPC is 0.16, which is modest but should be enhanced to nearly 0.5 inferred from measurements, setup margins presently indicate that 20MHz is possible.
My dream would be to reach 700M instructions so that the compiler would compile its biggest unit in about 10 seconds. But this is for now just a dream. If the 20MHz TAHX_InO comes to real silicon, it will be a nice 64 bits microcontroller for Ada execution.
Comments from software/hardware engineers on the LLIR, TAHX ISA… are welcome.
